This invention relates to an apparatus and a method for fabricating microminiature devices and, more particularly, to a variable-spot raster scanning technique for use in an electron beam exposure system.
U.S. Pat. No. 3,900,737, which issued to R. J. Collier and D. R. Herriott on Aug. 19, 1975, describes an electron beam exposure system (EBES) that is a practical tool for generating high-quality fine-featured integrated circuit masks. The system is also capable of exposing patterns directly on resist-coated semiconductor wafers. EBES combines continuous translation of the mask or wafer substrate with periodic deflection of the electron beam in a raster-scan mode of operation.
The EBES exposure process requires a beam of electrons emitted from a cathode to be focused to a submicron-size spot on an electron-sensitive resist layer. In practice, the diameter of the spot is also the address dimension of the system. In one particular practical embodiment of EBES, the electron beam is focused to a spot 0.5 micrometers (.mu.m) in diameter on the resist layer and is modulated on and off as the spot is successively scanned in raster fashion across a subregion of the layer. Each scan line of the raster has a width of one address dimension and a length of 256 address dimensions. Such a system meets important current needs for moderate-resolution devices (about 2-.mu.m linewidths with 0.5-.mu.m resolution) but does not illustrate the ultimate limits of the capabilities of EBES.
Various modifications of EBES are possible to adapt it to meet the increasing demand for devices with still smaller features. For example, if it is desired to write 1-.mu.m minimum features with 0.25-.mu.m resolution, using the EBES scanning mode described in the aforecited patent, an electron spot 0.25 .mu.m in diameter can be employed. However, the penalty that is thereby incurred is that the time required to expose a given area of the resist is increased by a factor of four. For many proposed applications of practical importance this is an economically burdensome penalty which is not acceptable. Thus, considerable effort has been directed at trying to devise a way in which to decrease the resolution or address dimension of EBES without at the same time increasing the pattern-writing speed of the system. Moreover, it was recognized that such a way, if available, would also increase the pattern-writing speed of EBES in its aforementioned moderate or 0.5-.mu.m resolution mode.